SystemC Libraries & Projects

This page gives an overview of open-source SystemC libraries and projects. Please let us know if a project or library is missing or needs update.


This is a list of SystemC models for use in virtual platforms:

Name Description License
NVIDIA Deep Learning Accelerator (NVDLA) SystemC TLM2.0-compatible virtual platform NVIDIA Open NVDLA License and Agreement v1.0
ParaNut Processor Customizable, highly scalable, and RISC-V compatible processor architecture for FPGA-based systems BSD-2-Clause
Virtual Components Modeling Library (VCML) Models The VCML productivity library contains many component models (ARM, RISC-V, Virtio, ...) Apache-2.0
Virtual Components Modeling Library (VCML) NVDLA Model VCML integration of the NVDLA model Apache-2.0
VPV-Peripherals Library of example SystemC/TLM peripherals for various SoCs based on the SCC library Apache-2.0

Productivity and Utility Libraries

The Productivity and utility libraries contain common resources, building blocks, and utilities that can be used for creation of SystemC-based virtual platforms, supporting different use cases such as software development, Architecture exploration, and High-Level Synthesis.

Name Description License
High-Level Synthesis Libs (HLSLibs) Repository for the unlimited length integer and fixed-point AC types usable with SystemC, plus math, DSP and ML building blocks, as well as SystemC MatchLib Apache-2.0
SystemC-Components (SCC) A light weight productivity library for SystemC and TLM 2.0 based modeling tasks using C++11 provides common functions, components and modules often needed in SystemC based models Apache-2.0
Virtual Components Modeling Library (VCML) Sockets, Tracing, Registers, GDB server, Logging, Session Protocol, Component Models, Network backends, TLM2.0 protocols Apache-2.0
sc-during Parallel programming on top of SystemC/TLM LGPLv2.1

Virtual Platforms and Virtual Prototypes

This is a list of open-source Virtual Platforms and Virtual Prototypes (VPs):

Name Description OS / Workloads License
SymEx-VP A concolic testing framework for RISC-V embedded software with support for SystemC peripherals. RIOT, Zephyr, NuttX, Zig GPLv3
ARMv8 Virtual Platform (AVP64) OCX QEMU-based ARMv8 multi-core VP CoreMark, Dhrystone, Linux, Xen hypervisor MIT
GreenSocs A53 VP ARM Cortex A53 multi-core VP (registration required) Linux GPLv2
GreenSocs N1 VP ARM Neoverse N1 multi-core VP (registration required) Linux GPLv2
GreenSocs RISC-V64 VP 64-bit RISC-V multi-core VP (registration required) Linux GPLv2
OpenRISC 1000 Multicore VP (OR1KMVP) OR1KISS-based multi-core OpenRISC1000 VP Linux Apache-2.0
TGC-VP The Scale4Edge ecosystem RISC-V VP FreeRTOS Apache-2.0
Xilinx Zynq-7000 QEMU based Xilinx Zynq-7000 SoC connected SystemC TLM 2.0 MIT

Compilers, parsers, and source-to-source transformations

Name Description License
Recoding Infrastructure for SystemC (RISC) Framework for analysis and agressive parallel simulation of embedded system models described in SystemC BSD-3-Clause
SystemC compiler Compiler which translates synthesizable SystemC design to synthesizable SystemVerilog design Apache-2.0
Verilator Compiler and simulator which translates Verilog/SystemVerilog to SystemC LGPLv3
systemc-clang Static analysis framework for RTL and TLM SystemC models including a HDL synthesis plugin that generates Verilog systemc-clang


Name Description License
SystemC SystemC Reference Implementation Apache-2.0
SystemC-AMS SystemC-AMS Proof-of-concept implementation Apache-2.0

Python Integration

Name Description License
PySysC A Python package to make SystemC usable from Python. It supports composition of a SystemC/TLM model as well as running the simulation. Apache-2.0


Name Description License
UVM-Connect UVM-based library that provides TLM1 and TLM2 connectivity and object passing between SystemC and SystemVerilog UVM models and components Apache-2.0
UVM-ML Universal Verification Methodology Multi-Language (UVM-ML) Open Architecture supporting UVM-SV, UVM-e, and UVM-SC Apache-2.0
UVM-SystemC Accellera implementation and standard of the Universal Verification Methodology (UVM) in SystemC Apache-2.0
CRAVE Constrained RAndom Verification Enviroment
NOTE: Join Accellera to get access to the latest version of this library
FC4SC Functional Coverage for SystemC
NOTE: Join Accellera to get access to the latest version of this library