SystemC Libraries & Projects

This page gives an overview of open-source SystemC libraries and projects. Please let us know if a project or library is missing or needs update.

Models

This is a list of SystemC models for use in virtual platforms:

Name Description License
NVIDIA Deep Learning Accelerator (NVDLA) SystemC TLM2.0-compatible virtual platform NVIDIA Open NVDLA License and Agreement v1.0
Virtual Components Modeling Library (VCML) Models The VCML productivity library contains many component models (ARM, RISC-V, Virtio, ...) Apache 2.0
Virtual Components Modeling Library (VCML) NVDLA Model VCML integration of the NVDLA model Apache 2.0
VPV-Peripherals Library of example SystemC/TLM peripherals for various SoCs based on the SCC library Apache 2.0

Productivity Libraries

Productivity libraries contain common resources and building blocks that can be used for High-Level Synthesis or the creation of SystemC-based virtual platforms.

Name Description License
High-Level Synthesis Libs (HLSLibs) Repository for the unlimited length integer and fixed-point AC types usable with SystemC, plus math, DSP and ML building blocks, as well as SystemC MatchLib Apache 2.0
SystemC-Components (SCC) A light weight productivity library for SystemC and TLM 2.0 based modeling tasks using C++11 provides common functions, components and modules often needed in SystemC based models Apache 2.0
Virtual Components Modeling Library (VCML) Sockets, Tracing, Registers, GDB server, Logging, Session Protocol, Component Models, Network backends, TLM2.0 protocols Apache 2.0

Virtual Platforms

This is a list of open-source Virtual Platforms (VPs):

Name Description Workloads License
ARMv8 Virtual Platform (AVP64) OCX QEMU-based ARMv8 multi-core VP CoreMark, Dhrystone, Linux, Xen hypervisor MIT
HIFIVE1-VP DBT-RISE-based RISC-V VP FreeRTOS BSD 3-Clause
OpenRISC 1000 Multicore VP (OR1KMVP) OR1KISS-based multi-core OpenRISC1000 VP Linux Apache 2.0
TGC-VP The Scale4Edge ecosystem RISC-V VP FreeRTOS Apache 2.0
Xilinx Zynq-7000 QEMU based Xilinx Zynq-7000 SoC connected SystemC TLM 2.0 MIT

Compilers

Name Description License
SystemC compiler Compiler which translates synthesizable SystemC design to synthesizable SystemVerilog design Apache 2.0
Verilator Compiler and simulator which translates Verilog/SystemVerilog to SystemC LGPL-3.0

Simulators

Name Description License
SystemC SystemC Reference Implementation Apache 2.0
SystemC-AMS SystemC-AMS Proof-of-concept implementation Apache 2.0

Python Integration

Name Description License
PySysC A Python package to make SystemC usable from Python. It supports composition of a SystemC/TLM model as well as running the simulation. Apache 2.0