EDA Tools supporting SystemC
This page gives an overview of electronics design automation tools and technologies supporting SystemC.
Please let us know if an EDA tool or technology is missing or needs update.
Industry Supported Tools
| Name | Company | Description |
|---|---|---|
| 360 DV-SC | Onespin | Formal verification of algorithmic and HLS models |
| Active HDL | Aldec | Windows based integrated FPGA Design Creation and Simulation solution |
| Catapult HLS | Siemens EDA | High-level synthesis of C/C++ or SystemC descriptions to RTL |
| CoFluent | Intel | System modeling and simulation solution to analyze performance properties |
| CyberWorkBench | NEC | High-level synthesis of C/C++ or SystemC descriptions to RTL |
| COSIDE | COSEDA | Integrated design environment for heterogeneous system modeling using SystemC and SystemC-AMS |
| Helium | Cadence | Integrated design environment to enable early pre-silicon software bring-up and concurrent hardware/software co-verification |
| Platform Architect | Synopsys | SystemC TLM 2.0 based graphical environment for early analysis and optimization of multicore SoC architectures for performance and power |
| Questa | Siemens EDA | Multi-language simulation environment supporting Verilog, SystemVerilog, VHDL, and SystemC |
| Riviera-PRO | Aldec | Multi-language simulation environment supporting Verilog, SystemVerilog, VHDL, and SystemC |
| Simulink Coder | Mathworks | SystemC/TLM component generator using the Simulink Coder |
| SIM-V | MachineWare | RISC-V full system simulator with SystemC TLM-2.0 interfaces |
| Stratus HLS | Cadence | High-level synthesis of C/C++ or SystemC descriptions to RTL |
| Tina | DesignSoft | Circuit Simulator for Analog, Digital, MCU and RF Circuits |
| VCS | Synopsys | Multi-language simulation environment supporting Verilog, SystemVerilog, VHDL, and SystemC |
| Virtualizer | Synopsys | Integrated design environment for the development and deployment of virtual prototypes |
| Vista | Siemens EDA | Integrated design environment for virtual prototyping, debugging, and analyzing of complex systems |
| VLAB | ASTC | Simulation environment to enable virtualization of embedded products, driving rapid design iterations across hardware and software |
| Xcelium | Cadence | Multi-language simulation environment supporting Verilog, SystemVerilog, VHDL, and SystemC |
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