SystemC Evolution Fika - 26 June 2025
Workshop on the Evolution of SystemC Standards
The SystemC Evolution Fika is a series of online workshops to discuss the latest SystemC developments and applications. We refer to these workshops as fikas, to honor the fika tradition of sharing a coffee, slowing down a bit, and talking about things that we care about.
Organization Team
- Martin Barnasconi, NXP
- Mark Burton, Qualcomm
- Jerome Cornet, STMicroelectronics
- Peter de Jager, Intel
- Nils Luetke-Steinhorst, Cadence
Program
Presentations will follow soon
| Time (CEST) | Title | Presenter(s) |
|---|---|---|
| 16:00 - 16:10 | Welcome & Introduction | Mark Burton, SystemC Fika Chair |
| 16:10 - 16:40 | DVCon Europe 2025 SystemC Modeling Challenge 🔗 Abstract |
Christoph Grimm, Rheinland-Pfälzische Technische Universität (RPTU) Germany Moritz Herzog, Rheinland-Pfälzische Technische Universität (RPTU) Germany |
| 16:40 - 17:10 | MEbots: Robotic Simulation using SystemC Abstract |
Sara Vinco, Politecnico di Torino Italy |
| 17:10 - 17:30 | SystemC CCI Summer of Code Abstract |
Antonios Salios, RWTH Aachen University Lukas Jünger, Machineware GmbH Germany |
| 17:30 - 18:00 | A SystemC-UVM testbench for a student lab exercise Abstract |
Thilo Vörtler, COSEDA Technologies Jens Schönherr, Hochschule für Technik und Wirtschaft Dresden Germany |
| 18:00 - 18:10 | Q&A and Closing | Mark Burton, SystemC Fika Chair |
Abstracts
DVCon Europe 2025 Modeling Challenge: Power-Aware Simulation
Presenters: Christoph Grimm, Moritz Herzog, Rheinland-Pfälzische Technische Universität (RPTU) Germany
Power and energy consumption is nowadays one of the key performances of HW/SW Systems.
However, knowing and understanding the power and energy consumption is often a blind spot in the development.
This holds in particular early in the development and at high level of abstraction, during development of firmware, and finally in the case of power or signal integrity issues.
In the presentation we will give an overview of the state of the art and discuss ways to integrate power-awareness in SystemC simulations.
Furthermore, we will explain the DVCon Europe 2025 Modeling challenge that deals with this topic.
Besides the good chances to win some of the many prizes like notebooks and traveling grants to support participants in joining DVCon Europe 2025.
Also, all participants will get certificates that document their participation and contribution.
MEbots: Robotic Simulation using SystemC
Presenter: Sara Vinco, Politecnico di Torino Italy
The heterogeneous and extensible nature of SystemC—particularly when combined with its TLM and AMS extensions—makes it a powerful foundation for modeling Cyber-Physical Systems (CPS). This talk will present a novel integration of SystemC-based virtual platforms with robotic simulators. The goal is to enable holistic virtual prototyping with support for both functional behavior and extra-functional metrics—especially energy consumption and environmental interaction. This integration paves the way for early design space exploration and optimization of power-aware control strategies in robotics.
SystemC CCI Summer of Code
Presenters: Antonios Salios, RWTH Aachen University; Lukas Jünger, Machineware GmbH Germany
The Summer of Code CCI project aims to develop a modular, extensible control API as part of the SystemC CCI library, enabling interactive simulation management. Early work has focused on CI pipeline improvements, golden file validation for test outputs, and resolving C++20 compatibility issues. Current efforts include integrating the experimental inspection library into the core framework and drafting an initial design for the control interface.
A SystemC-UVM testbench for a student lab exercise
Presenters: Thilo Vörtler, COSEDA Technologies; Jens Schönherr, Hochschule für Technik und Wirtschaft Dresden Germany
A short update is given on the current developments in the Accellera SystemC Verification Working Group, including UVM-SystemC, CRAVE, FC4SC, and announcement of public UVM SystemC repository.
Verification topics are becoming increasingly important in the course of study. SystemC with UVM is ideal for studying constrained random simulation, as UVM is industry standard, the libraries are freely available, and C++ skills are already present. This presentation introduces a test bench that students can use to learn this type of simulation.