SystemC Evolution Fika - 7 April 2022
Workshop on the Evolution of SystemC Standards
In 2022 we are continuing the SystemC Evolution by organizing a series of online workshops to discuss the latest SystemC developments and applications. We refer to these workshops as fikas, to honor the fika tradition of sharing a coffee, slowing down a bit, and talking about things that we care about.
Organization Team
- Ola Dahl, Ericsson (Chair)
- Martin Barnasconi, NXP
- Jerome Cornet, STMicroelectronics
- Christian Sauer, Cadence
- Mark Burton, GreenSocs
- Peter de Jager, Intel
Agenda
Main theme of the event: Parallelization of SystemC simulations
| Time (CEST) | Title | Presenter(s) | Affiliation(s) |
|---|---|---|---|
| 16:00 - 16:10 | Introduction Presentation | Video |
Ola Dahl | Ericsson, Stockholm, Sweden |
| 16:10 - 16:30 | sc-during: Parallel Programming on Top of SystemC Abstract | Presentation | Video |
Matthieu Moy | Laboratoire d’Informatique du Parallélisme (LIP), Lyon, France |
| 16:30 - 16:50 | Ensuring reproducible parallel LT TLM models simulation with SCale SystemC kernel Abstract | Presentation | Video |
Tanguy Sassolas | CEA - LIST, Gif-sur-Yvette, France |
| 16:50 - 17:10 | The Intel Simics Simulator and SystemC and Threading Abstract | Presentation | Video |
Jakob Engblom | Intel, Stockholm, Sweden |
| 17:10 - 17:30 | RISC: A Compiler for Parallel SystemC with Maximum Standard Compliance Abstract | Presentation | Video |
Rainer Dömer | University of California, Irvine, CA, USA |
| 17:30 - 18:00 | Discussion Video |
All participants. Moderator: Ola Dahl |
Abstracts
sc-during: Parallel Programming on Top of SystemC
Presenter: Matthieu Moy, Laboratoire d’Informatique du Parallélisme (LIP), Lyon, France
The SystemC/TLM technologies are widely accepted in the industry for fast system-level simulation. An important limitation of SystemC regarding performance is that the reference implementation is sequential, and the official semantics makes parallel executions difficult. We propose an approach that explicitly targets loosely timed systems, and offers the user a set of primitives to express tasks with duration, as opposed to the notion of time in SystemC which allows only instantaneous computations and time elapses without computation. Our tool exploits this notion of duration to run the simulation in parallel. It runs on top of any (unmodified) SystemC implementation, which lets legacy SystemC code continue running as-it-is. This allows the user to focus on the performance-critical parts of the program that need to be parallelized.
More information: https://matthieu-moy.fr/spip/?sc-during-Parallel-Programming-on-Top-of-SystemC
Ensuring reproducible parallel LT TLM models simulation with SCale SystemC kernel
Presenter: Tanguy Sassolas, CEA - LIST, Gif-sur-Yvette, France
To meet virtual prototyping simulation needs for the design of complex SoC, several techniques (TLM, DMI, temporal decoupling) were used to abstract the modelling while maintaining the sequential evaluation stemming from SystemC standard coroutine approach. Parallelization of models at this level of abstraction requires ensuring atomic evaluation of all sc_threads to maintain expected model behavior and ensure reproducible simulation, key to guest software debugging. This presentation will detail how the SCale SystemC kernel tackles this issue through efficient monitoring of sc_thread’s accesses to shared resources and process-level rollback when necessary.
More information: https://hal.archives-ouvertes.fr/hal-03487607/documen
The Intel Simics Simulator and SystemC and Threading
Presenter: Jakob Engblom, Intel Corporation, Stockholm, Sweden
This presentation gives a short introduction to the threading model used in version 6 of the Intel® Simics® simulator, and how SystemC subsystems are integrated into it. The Simics framework supports running multiple different SystemC subsystems in parallel, using the Simics simulator core threading mechanisms. The requirement to stick to standard SystemC kernel semantics imposes some limitations on the available parallelism.
More information: https://www.intel.com/content/www/us/en/developer/articles/tool/simics-simulator.html
RISC: A Compiler for Parallel SystemC with Maximum Standard Compliance
Presenter: Rainer Dömer | University of California, Irvine, CA, USA
We briefly review the major obstacles that stand in the way of standard-compliant parallel SystemC simulation and then present the Recoding Infrastructure for SystemC (RISC), which is a compiler-based approach to overcome these obstacles. RISC enables the parallel simulation of unmodified SystemC models with maximum standard compliance. Reference: R. Dömer: "Seven Obstacles in the Way of Standard-Compliant Parallel SystemC Simulation", IEEE Embedded Systems Letters, vol. 8, no. 4, pp. 81-84, December 2016.
More information: https://www.cecs.uci.edu/~doemer/risc.html