SystemC Evolution Fika - March 2021
The first SystemC Evolution Fika took place on 17 March 17 2021. Two presentations were given; one on SystemC and Python and one about the Intel SystemC Compiler. See the abstracts and slides below.
You are all welcome to join the next SystemC Evolution Fika! If you have topics that you think should be included in upcoming fikas, please let us know at systemc-evolution-fika@lists.accellera.org.
Event information
Date: 17 March 2021
Time: 16:00 - 18:00 CET
Location: Online event
Organization Team
- Ola Dahl, Ericsson (Chair)
- Martin Barnasconi, NXP
- Jerome Cornet, STMicroelectronics
- Christian Sauer, Cadence
- Mark Burton, GreenSocs
- Peter de Jager, Intel
Agenda
| Time (CEST) | Title | Presenter(s) | Affiliation(s) |
|---|---|---|---|
| 16:00 - 17:00 | Python and SystemC Abstract | Presentation |
Rocco Jonack1 Eyck Jentzsch2 |
1Arteris 2MINRES Technologies |
| 17:00 - 18:00 | Intel Compiler for SystemC Abstract | Presentation |
Mikhail Moiseev | Intel |
Presentation Abstracts
Python and SystemC
Presenters: Rocco Jonack, Arteris; Eyck Jentzsch, MINRES Technologies
Scripting is commonly used in today's applications and EDA tools. For SystemC various proprietary and open source solutions are available. All of them impose various constraints on SystemC users and often restrict the visibility of C++ components to Python. We present a novel approach of integrating SystemC. It does not require any instrumentation or manual preparation and exposes all SystemC types and functions as well as components provided by other libraries, i.e. IP libraries (even in binary form). It allows calling Python from SystemC modules e.g. to implement scriptable components for verification purposes. The session will outline how this can be used to implement interactive and dynamic tools to assemble Virtual prototypes (VP) easily as well as control their simulation. This is especially useful in HW/SW unit testing and FW verification where the dynamic nature of Python allows to select various test cuts of the VP to ease the tasks.
Intel Compiler for SystemC
Presenter: Mikhail Moiseev, Intel
Intel® Compiler for SystemC (ICSC) translates synthesizable SystemC design to synthesizable SystemVerilog design.
ICSC supports SystemC synthesizable subset in method and thread processes and arbitrary C++ code in module constructors. The tool produces human-readable SystemVerilog for complex multi-module designs in tens of seconds. This tool is focused on improving productivity of design and verification engineers and leaves optimization work for an underlying logic synthesis tool. It performs design checks to detect non-synthesizable code and common coding mistakes. ICSC is based on LLVM/Clang frontend, that allows to support modern C++ standards.
ICSC has a common library which includes collections of FIFOs, clock gate cells, zero-delay channels and others. ICSC supports SystemC immediate and temporal assertions translation into SystemVerilog Assertions (SVA).
The Intel® Compiler for SystemC is available at https://github.com/intel/systemc-compiler
The Very First SystemC Evolution Fika 
The first SystemC Evolution Fika was held on March 17, 2021. It was a virtual event, hosted by Accellera's Webex, with around 80 participants. We had two presentations on SystemC-related topics - Python and SystemC by Rocco Jonack and Eyck Jentzsch, and Intel Compiler for SystemC by Mikhail Moiseev.
Using Python together with SystemC, it is possible to express simulator configuration, with model instantiations and model connections, in Python. This gives a flexible environment which can be combined with other Python tools, in areas such as computation or graphical visualization.
The Python/SystemC combination presented at the Fika, which is available via Accellera's GitHub, can also be combined with the Minres SCC productivity library.
The Intel Compiler for SystemC translates SystemC to synthesizable SystemVerilog. With a focus on improving productivity in design and verification, it supports modern variants of C++ and the SystemC Synthesizable Standard. It generates human-readable SystemVerilog code, and it can be built using CMake. It also supports more advanced verification features, such as assertions and temporal assertions, which are translated from SystemC (C++) to corresponding SystemVerilog assertions. The Intel Compiler for SystemC is available via Intel's GitHub.
We would like to thank the speakers, and the participants, for this first Fika!
We are planning the next one, and we are always open to suggestions for topics for upcoming Fikas. You can reach us on systemc-evolution-fika@lists.accellera.org
Ola Dahl, on behalf of the SystemC Evolution Team
If you have a contribution in this area, please let us know at systemc-evolution-fika@lists.accellera.org.